1. Field of the Invention
The present invention relates to a voltage regulating device. More particular, the present invention relates to a voltage regulating device that is implemented by a low voltage CMOS manufacturing process and capable of enduring a high voltage output.
2. Description of the Related Art
Due to highly developed technology of VLSI process for CMOS devices, the sizes of transistors become more compact and their operation voltage are also considerably reduced. However, due to specification and noise margin, voltage signals outputted from an IC chip are usually higher than voltage signals inside the IC chip when the voltage signals are transmitted between IC chips. For example, the voltage signals inside the IC chip may be 0Vxcx9c1.5V, but its output voltage signals may be 0Vxcx9c2.5V. Accordingly, in practice, it needs a voltage level regulator to regulate lower voltage signals (such as 0Vxcx9c1.5V) inside the IC chips into higher voltage signals (such as 0Vxcx9c2.5V).
Generally speaking, transistors made by more advanced CMOS manufacturing process, the voltage endured between two electrodes of the transistor becomes lower and lower. Namely, the operation voltage between the gate and source (VGS), or the operation voltage between the gate and drain (VGD) falls with a lower voltage range. Therefore, it must use a transistor that can be operated in higher voltages, such as a dual-gate transistor, during the voltage regulating process from lower voltage signals to higher voltage signals. However, the transistors having higher operation voltages usually consume more powers and heats. In order to improve such defects, a voltage level regulating device made by the low voltage CMOS manufacturing process, as shown in FIG. 1, is provided such that VGS and VGD of each transistor are in the accessible range of the low voltage CMOS manufacturing process and the chip can output high voltages.
FIG. 1 shows an output stage of an I/O circuit according to a conventional art. Referring to FIG. 1, the voltage signal in the IC chip is a low voltage signal 130 having a range of 0Vxcx9cVDD, and VDD is 1.5V for example. The output voltage of the chip is 0Vxcx9cVCC, and VCC is 2.5V for example, wherein VCC greater than VDD greater than VCC/2. In practice, voltage VCC is greater than maximum endurable voltage for voltages VGS, VGD of the transistor in the low voltage CMOS manufacturing process. Preventing transistors from damage, it must envisage the voltage endurance issues to improve circuit structure. According to the conventional method, gates of two transistors MPC and MNC are biased at VCC/2 and both interposed between transistors MPD and MND that serve as an output stage for an I/O circuit, wherein VCC/2 is less than maximum endurable voltage for voltages VGS, VGD of the transistor in the low voltage CMOS manufacturing process. FIG. 1 shows two voltage level regulating device, one of which is a voltage level rising regulator 110 and the other is voltage level lowering regulator 120. The voltage level rising regulator 110 is used for regulating the voltage signals inside the IC chip from 0Vxcx9cVCC to VCCxcx9cVCC/2 and then transmitting them to the gate of the transistor MPD, while the voltage level lowering regulator 120 is used for regulating the voltage signals inside the IC chip from 0Vxcx9cVCC to VCC/2xcx9c0 and then transmitting them to the gate of the transistor MND. Accordingly, the voltages VGS and VGD of the transistors MPD, MND, MPC and MNC can be controlled without exceeding VCC/2, for preventing the transistors from damages due to high operation voltages.
When the voltage signal inside the IC chip is 0V, the output voltage VCC of the voltage level rising regulator 110 causes the transistors MPD, MPC to be turned off and the output voltage VCC/2 of the voltage level lowering regulator 120 causes the transistors MND, MNC to be turned on, by which the output voltage of the IC chip becomes 0V. In contrast, when the voltage signal inside the IC chip is VDD, the output voltage VCC/2 of the voltage level rising regulator 110 causes the transistors MPD, MPC to be turned on and the output voltage 0V of the voltage level lowering regulator 120 causes the transistors MND, MNC to be turned off, by which the output voltage of the IC chip becomes VCC.
As described above, when the voltage signal inside the IC chip is 0V, the IC chip outputs a voltage of 0V, and when the voltage signal inside the IC chip is VDD, the IC chip outputs a voltage of 0VCC. Therefore, it can be learned that the voltage level rising regulator 110 is used for converting the low voltage signal 130 into a high voltage signal 140 having a range of VCCxcx9cVCC/2, while the voltage level lowering regulator 120 is used for converting the low voltage signal 130 into a lower voltage signal having a range of VCC/2xcx9c0V.
FIG. 2 shows the function of the voltage level rising regulator. The voltage level rising regulator 110 can covert the low voltage signal 130 into the high voltage signal 140, in which the low voltage signal 130 is between a low level 131 of the low voltage signal 130 and a high level 135 of the low voltage signal 130 and the high voltage signal 140 is between a low level 141 of the high voltage signal 140 and a high level 145 of the high voltage signal 140. For example, the low voltage signal 130 can the voltage signal inside the IC chip, and low level 131 is 0V, the high level 135 is VDD, the high voltage signal 140 is the output of voltage level rising regulator 110, the low level 141 is VCC/2, and the high level 145 is VCC.
It should be noted that voltage level rising regulator 110 is implemented by the low voltage CMOS manufacturing process and output voltages of VCCxcx9cVCC/2. However, VCC has exceeded the voltage endurances for VGS, VGD of the low voltage CMOS manufacturing process. During circuit design, it must guarantee that VGS, VGD of each transistor in voltage level rising regulator 110 are operated within an allowable voltage range in order that the circuit can be normally worked. Therefore, one of solutions for solving this issue, shown in FIG. 3, is provided.
FIG. 3 shows a conventional voltage level rising regulator, which is published on IEEE JSSC, November, 1999. Metal-oxide-semiconductor (MOS) transistor is extensively used in integrated circuits and it usually uses PMOS to denote a P-type MOS transistor and NMOS to denote a N-type MOS transistor. According to the disclosure, the maximum voltage endurance is 2.4V for VGS and VGD of the CMOS transistors. When the voltage VDD of the output stage of the I/O circuit is 3.3V , the amplitude of input voltage of the voltage level rising regulator is 0Vxcx9c1.8V. The pbias terminal voltage is 1.1V, the pdrive output voltage is 3.3Vxcx9c(1.1+Vtp), wherein is the threshold voltage of PMOS transistors TP3, TP4, and the en 18_buffered voltage is 0V.
When the gate voltage of the transistor TN1 is 1.8V, voltages at nodes node1 and node2 are 0V. Theoretically, because the transistor TP3 is biased at pbias, the terminal voltage of pdrive is pulled down to pbias +Vtp. Considering the subthreshold leakage and well leakage, the terminal voltage of pdrive is perhaps pulled down to 0, and then VGS of the transistors Tp1 and TP2 exceeds maximum endurable voltage drop 2.4V. Therefore, a transistor TP5 is used for pulling up current, for avoiding voltage pdrive from dropping below pbias. When the voltage fed to the transistor TN1 is 0V, the voltages at node node2 and node4 become 0V. As a result, voltage pdrive is pulled down to pbias +Vtp to turn on the transistor TP1 and then pulls the voltage pdrive up to 3.3V.
Accordingly, in the conventional circuit, the transistors TP3, TP4 are used to avoid transistors TP1, TP2 from operating under high VGS and VGD. Similarly, the transistors TN3, TN4 are used to avoid transistors TN1, TN2 from operating under high VGS and VGD.
In summary, using the circuit mentioned above, low voltage signals are regulated to high voltage signals. The low voltage signals are between a low level (0V) of the low voltage and a high level (VDD) of the low voltage, and fed to the gate of the transistor TN1. The high voltage between a low level (pbias +Vtp) of the high voltage and a high level (0VDD) of the high voltage appears at pdrive. When the low level (0V) of the low voltage is fed to the circuit, the pdrive outputs the high level (0VDD) of the high voltage, and when the high level (VDD) of the low voltage is fed to the circuit, the pdrive outputs the low level (pbias +Vtp) of the high voltage.
In regard to the conventional voltage level rising regulator, there are several drawbacks. First, when the transistor TN1 is turned on, the voltage pdrive becomes pbias +Vtp. And at the same time, as described, the transistors TP5, TP3, TN3 and TN1 are turned on, causing a DC current flows from power 0VDD through the transistors TP5, TP3, TN3 and TN1 to ground GND. In addition, when the transistor TN2 is turned on, the transistors TP6, TP4, TN4 and TN2 are turned on, causing a DC current flows from power 0VDD through the transistors TP6, TP4, TN4 and TN2 to ground GND. Therefore, during the voltage level conversion, no matter what the conductive path is, there always existing a DC current flowing between a high voltage (the 0VDD) and a low voltage level (the ground), causing over consumption of the static power.
Secondly, the output level of the pdrive terminal is between pbias +Vtp and 0DD, meaning that logic xe2x80x9c0xe2x80x9d represented by pbias +Vtp varies with manufacturing parameters and cannot be accurately determined. For fixing the voltage level of the logic xe2x80x9c0xe2x80x9d, it needs to adjust the voltage pbias, causing complexity of operation.
Accordingly, it is an objective of the present invention to provide a voltage level rising regulator, which is a device for converting a low voltage signal into a high voltage signal, wherein the high voltage signal is between a low level and a high level. No matter what the condition is no current path is formed between supply voltages of the high level and the low level in the circuit of the device, thus effectively preventing generation of DC currents and static power consumption.
It is another objective of the invention to provide a voltage level rising regulator, which is a device for converting a low voltage signal into a high voltage signal, wherein the high voltage signal is between a low level and a high level. The device outputs the low level of the high voltage signal through the drain and source of a transistor such that the low level of the high voltage signal can be accurately defined and not affected by manufacturing parameters.
According to above objectives of the invention, it provides a voltage level rising regulator and its operating method set forth as follows.
A low voltage signal of 0V is inputted to a drain of a first NMOS transistor to turn it on, and through the source of the first NMOS transistor the 0V voltage is applied to a gate of a first PMOS transistor. The source of the first PMOS transistor is connected to a voltage of 1.25V. As the 0V voltage is inputted to the gate of the first PMOS transistor, the first PMOS transistor is turned on. Therefore, the drain of the first PMOS transistor is also 1.25V and that is further applied to another PMOS transistor, a second PMOS transistor. The source of the second PMOS transistor is connected to a voltage of 2.5V. As the 1.25V voltage is inputted to the gate of the second PMOS transistor, the second PMOS transistor is turned on. Therefore, the drain of the second PMOS transistor is also 2.5V. Accordingly, the drain of the second PMOS transistor can be used as the output of the regulator, by which when a low voltage signal of 0V voltage is inputted, a 2.5V voltage, i.e. the high level of the high voltage signal, is outputted.
On the other hand, when a low voltage signal of 1.5V is applied to the regulator, this low voltage signal is inverted to a voltage of 0V by an inverter. The inverted low voltage signal is further inputted to a drain of a second NMOS transistor to turn on the second NMOS transistor, by which the 0V voltage is applied to the gate of a third PMOS transistor. The source of the third PMOS transistor can be connected to 1.25V. As the 0V voltage is inputted to the gate of the third PMOS transistor, the third PMOS transistor is turned on such that the drain and the source of the third PMOS transistor are 1.25V. Accordingly, the drain of the third PMOS transistor can be the output of the regulator, by which when the low voltage signal of 1.5V voltage is inputted, a 1.25V voltage, i.e. the low level of the high voltage signal, is outputted.